VBUS054CD-FHI www.vishay.com vishay semiconductors rev. 1.4, 31-may-12 1 document number: 81882 for technical questions, contact: esdprotection@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 4-line bus-port esd-protection - flow through design marking (example only) dot = pin 1 marking yy = type code (see table below) xx = date code features ? compact llp2513-11l package ? low package height < 0.6 mm ? 4-line esd-protection ? low leakage current i r < 0.1 a ? low load capacitance c d = 0.8 pf ? ideal for high speed data line like - hdmi, displayport, esata - usb, 1394/firewire ? esd-protection acc. iec 61000-4-2 15 kv contact discharge 15 kv air discharge ? soldering can be checked by standard vision inspection. no x-ray necessary ? e4 - precious metal (e.g. ag , au, nipd, nipdau) (no sn) ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 21324 21326 gnd nc. nc. nc. nc. gnd d2 + d2 - d1 + d1 - 11 12345 10 9 8 76 yyxx 20720 ordering information device name ordering code taped units per reel (8 mm tape on 7" reel) minimum order quantity VBUS054CD-FHI VBUS054CD-FHI-gs08 3000 15 000 package data device name package name type code weight molding compound flammability rating moisture sensitivity level soldering conditions VBUS054CD-FHI llp2513-11l 9x 5.5 mg ul 94 v-0 msl level 1 (according j-std-020) 260 c/10 s at terminals absolute maximum ratings parameter test conditions symbol value unit peak pulse current acc. iec 61000-4-5; t p = 8/20 s; single shot i ppm 3.5 a peak pulse power acc. iec 61000-4-5; t p = 8/20 s; single shot p pp 45 w esd immunity contact discharge acc. iec 61000-4-2; 10 pulses v esd 15 kv air discharge acc. iec 61000-4-2; 10 pulses v esd 15 kv operating temperature junction temperature t j - 40 to + 125 c storage temperature t stg - 55 to + 150 c
VBUS054CD-FHI www.vishay.com vishay semiconductors rev. 1.4, 31-may-12 2 document number: 81882 for technical questions, contact: esdprotection@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 application note the VBUS054CD-FHI is a four-line esd-protection device with the characte ristic of a z-diode with a high esd-immunity and a very low capacitance which makes it usable for hi gh frequency applications like usb2.0 or hdmi. with the VBUS054CD-FHI four high speed data lines can be protected against transient voltage signals like esd (electro static discharge). connected to the data line (pin 1, 2 and pin 4, 5) an d to ground (pin 3, 8 and 11) negative transients will be clam ped close below the ground level while positive transients will be clamped close above the 5 v working range. the clamping behaviour of the VBUS054CD-FHI is bidirectional but asymmetrical ( bias ) and so it offers the best protection for applications running up to 5 v. pin configuration: ? pin 3, 8 and 11 are internally shorted and have to be connected to ground ? pin 1, 2 and 4, 5 are the inputs for the data lines d 1+ and d 1- and d 2+ and d 2- ? pin 6, 7 and 9, 10 are not connected internally flow through design modern digital transmission lines can be clocked up to 480 mbit/s (usb2.0) or 1.65 gbit/s (hdmi). at such high data rates the transmission lines like cables or the line traces on the pcbs have to be very homogeneous regarding their surge impedance. th is requires well defined trace dime nsions as trace width and distance which have to be calculated depending on the requested surge impedance (e.g. 50 ? ) and the pcb material and layer dimensions. any device connected to the data lines - like esd-protection devi ces - have to be connected with minimal changes in these trace dimensions and distances. with the package in the so called flow through design this is possible. the lines are running straight along the pcb while th e VBUS054CD-FHI is placed on top without any vias or loops. electrical characteristics (pin 1, 2, 4 or 5 to pin 3) (t amb = 25 c, unless otherwise specified) parameter test conditions/remarks symbol min. typ. max. unit protection paths number of li nes which can be protected n channel --4lines reverse stand-off voltage max. reverse working voltage v rwm --5v reverse voltage at i r = 0.1 a v r 5--v reverse current at v rwm = 5 v i r - < 0.01 0.1 a reverse breakdown voltage at i r = 1 ma v br 6.9 7.9 8.7 v reverse clamping voltage at i pp = 1 a v c -9.111v at i pp = i ppm = 3.5 a v c - 11.6 13 v forward clamping voltage at i pp = 1 a v f -1.62.4v at i pp = 3.5 a v f -3.55 v capacitance at v r = 0 v; f = 1 mhz c d -0.81pf 21326 gnd nc. nc. nc. nc. gnd d2 + d2 - d1 + d1 - 11 12345 10 9 8 76 matched pair matched pair gnd d2 + d2 - d1 + d1 - i/o port connector usb/hdmi interface d1 + d1 - d2 + d2 - 21328 12345 10 9 8 7 6 11
VBUS054CD-FHI www.vishay.com vishay semiconductors rev. 1.4, 31-may-12 3 document number: 81882 for technical questions, contact: esdprotection@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (t amb = 25 c, unless otherwise specified) fig. 1 - esd discharge current wave form acc. iec 61000-4-2 (330 ? /150 pf) fig. 2 - 8/20 s peak pulse current wave form acc. iec 61000-4-5 fig. 3 - typical capacitance c d vs. reverse voltage v r fig. 4 - typical forward current i f vs. forward voltage v f fig. 5 - typical reverse voltage v r vs. reverse current i r fig. 6 - typical peak clamping voltage v c vs. peak pulse current i pp 0 % 20 % 40 % 60 % 80 % 100 % 120 % - 10 0 10 20 30 40 50 60 70 80 90 100 time (ns) discharge current i esd rise time = 0.7 ns to 1 ns 53 % 27 % 20557 0 % 20 % 40 % 60 % 80 % 100 % 010203040 time (s) i ppm 20 s to 50 % 8 s to 100 % 20548 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 012345 v r at pin 1 and pin 4 (v) c d (pf) 22348 f = 1 mhz v r at pin 2 or pin 3 = 0 v v r at pin 2 or pin 3 = 3.3 v 0.001 0.01 0.1 1 10 100 0.5 0.6 0.7 0.8 0.9 1 1.1 pin 3 to pin 1, 2, 4 or 5 22349 v f (v) i f (ma) 0 1 2 3 4 5 6 7 8 9 0.01 0.1 1 10 100 1000 10 000 pin 1, 2, 4 or 5 to pin 3 22350 i r (a) v r (v) 0 2 4 6 8 10 12 14 012345 measured acc. iec 61000-4-5 (8/20s - wave form) v c pin 1, 2, 4 or 5 to pin 3 pin 3 to pin 1, 2, 4 or 5 21477 i pp (a) v c (v)
VBUS054CD-FHI www.vishay.com vishay semiconductors rev. 1.4, 31-may-12 4 document number: 81882 for technical questions, contact: esdprotection@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 7 - typical clamping performance at + 8 kv contact discharge (acc. iec 61000-4-2) fig. 8 - typical clamping performance at - 8 kv contact discharge (acc. iec 61000-4-2) fig. 9 - typical peak clamping voltage at esd contact discharge (acc. iec 61000-4-2) - 20 0 20 40 60 80 100 - 10 0 10 20 30 40 50 60 70 80 90 t (ns) v c-esd (v) 22352 acc. iec 61000-4-2 + 8 kv contact discharge - 120 - 100 - 80 - 60 - 40 - 20 0 20 - 10 0 102030405060708090 t (ns) v c-esd (v) 22353 acc. iec 61000-4-2 - 8 kv contact discharge - 200 - 150 - 100 - 50 0 50 100 150 200 0 5 10 15 20 v esd (kv) v c-esd (v) 22354 positive discharge negative discharge acc. iec 61000-4-2 contact discharge v c-esd
VBUS054CD-FHI www.vishay.com vishay semiconductors rev. 1.4, 31-may-12 5 document number: 81882 for technical questions, contact: esdprotection@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 package dimensions in millimeters (inches): llp2513-11l solder resist mask solder pad 0.5 (0.020) 0.25 (0.010) 4 x 0.5 = 2 (0.079) 0.15 (0.006) 0.37 (0.015) 0.22 (0.009) 2.55 (0.100) 2.45 (0.096) pin 1 marking 0.05 (0.002) 0 (0.000) 0.152 (0.006) ref. 2 (0.079) ref. 0.25 (0.010) 0.19 (0.007) 0.5 (0.020) bsc 0.28 (0.011) 0.22 (0.009) 1.4 (0.055) 1.3 (0.051) 0.6 (0.024) 0.5 (0.020) 0.4 (0.016) 0.4 (0.016) 21382 created - date: 15. april 2008 document no.:s8-v-3906.04-009 (4) rev. 2 - date: 09. sep. 2008 foot print recommendation:
VBUS054CD-FHI www.vishay.com vishay semiconductors rev. 1.4, 31-may-12 6 document number: 81882 for technical questions, contact: esdprotection@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pin 1 - location top view pad layout - view from top s een at bottom s ide llp1713 llp2513 llp3313 pin 1 - location pin 1 - location top view top view pad layout - view from top s een at bottom s ide pad layout - view from top s een at bottom s ide
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